module d_flip_flop(Clk_50M, Rst_n, D, Q);

	input Clk_50M;
	input Rst_n;
	input D;
	output reg Q;
	
	//D触发器的逻辑
	always@(posedge Clk_50M or negedge Rst_n) begin
		if(Rst_n == 1'b0) begin
			Q <= 1'b0;
		end
		else begin
			Q <= D;
		end
	end
endmodule
